1. Field of the Invention
This invention relates to the design of integrated circuits. More particularly, it relates to the design of input and output buffers in an integrated circuit.
2. Background of Related Art
Integrated circuits are an important part of life as we know it today. They are the basis for most all electronic device, from telephones and answering machines to the most sophisticated computers. An important part of an integrated circuit (IC) is its ability to accept information in, and/or to pass information out. Thus, an IC must interface with the outside world.
While direct electrical connection with internal components of an IC is possible, it would leave the IC vulnerable to external voltages and currents, which may exceed the ability of the internal circuit. To provide both protection of internal components from external signals, as well as to provide amplified output signals, most signals input or output on a typical IC interfacing with the external world are ‘buffered’.
A buffer is usually a more robust circuit capable of handling typical external signal levels, as well as capable of driving a given number of connections to other devices.
Though a necessary evil, buffers can prove to be a gating element of a high speed connection. In particular, while internal circuitry may be extremely fast operating, a buffer may be slower because of its relatively larger size to provide suitable protection as well as drive a suitable level of output current.
The slew rate of a buffer can be defined as the maximum rate that the output voltage of a buffer can change. Slew rate causes distortion for high frequency large signal operation. High slew rates are good from a signal standpoint as it means that the output of a buffer very quickly follows the input signal to that buffer, but it comes at the price of increased transient noise in the system. Some exemplary noise includes overshoot or undershoot of the signal beyond the desired output level caused by the very rapid ascension or fall to that level.
To balance the needs of speed of output versus the need for avoiding increased electrical noise in a circuit, CMOS buffers have been developed that allow the output slew rate to be switched between two pre-determined values. The user is given the ability to select a high slew rate to run at maximum speed, and a low slew rate to reduce noise when the maximum speed is not needed.
For instance, FIG. 3 shows a conventional tri-statable CMOS output buffer.
As shown in FIG. 3, a conventional buffer includes an output drive stage consisting of p-channel transistor M1 and n-channel transistor M2. The conventional buffer also has a pre-drive section consisting of p-channel transistors M3 and M9 and n-channel transistors M4 and M10, an AND gate X1, an OR gate X2, and an inverter X3. An input signal A is input to the buffer, as is an enable signal EN. The buffer creates an output signal PAD.
When the enable signal EN is valid or HIGH, the output of the buffer follows the logic level of the input A. When the enable signal EN is invalid or LOW, node P is high and node N is LOW, turning OFF both output transistors M1 and M2 in the output drive stage. For the purposes of clarity in this disclosure, it will be understood for the remainder of this discussion that the buffer is enabled (e.g., with HIGH enable signal EN).
The slew rate of the output signal PAD from the buffer is controlled by the speed at which nodes N and P are switched. If node N is quickly switched high by transistor M9, then transistor M2 will be quickly turned ON, resulting in a large slew rate for the high-to-low transition on the output signal PAD. Likewise, if node P is quickly pulled low by transistor M4, then transistor M1 will be quickly turned ON, resulting in a large slew rate for the low-to-high transition on the output signal PAD.
To achieve maximum speed, the pre-drive stage devices, such as the gate width of MOS pre-drive stage transistors, should be equal to about ⅓ the size of the devices of the stage that it is driving. Typical sizes of transistor M1 and transistor M2 for a high drive output could be as large as 600 um (channel width) for transistor M1, and as large as 300 um (channel width) for transistor M2. Thus, typical sizes for the channel width of transistor M3 would be 200 um, for transistor M4 would be 100 um, for transistor M9 would be 100 um, and for transistor M10 would be 50 um.
The downside of high speed operation with such a buffer is that higher slew rates necessary to achieve such high speed operation will cause more electrical noise such as transient noise in the integrated circuit. Such noise is often carried through many parts of the IC, e.g., through a power and/or ground rail. Thus, designers are often faced with a design choice between a given IC with buffers that provide a certain high slew rate at the price of higher electrical noise, and another IC with buffers that provide a lower slew rate and lower electrical noise.
In practice, many IC users want the ability to use a single chip in multiple applications. For instance, the designer might become familiar with certain aspects of a given IC, and favor it in multiple applications. In other cases, manufacturing inventory may be minimized by utilizing a same IC in multiple applications. In some of these applications, an IC with specific buffers may have to operate at high switching speeds necessitating high slew rates, but in other applications the same buffer could run at lower switching speeds utilizing lower slew rates to provide a quieter system. Thus, buffers that have a selectable slew rate were developed.
For instance, FIG. 4 shows a conventional circuit that allows the slew rate of a buffer to be switched between higher and lower slew rates.
In particular, as shown in FIG. 4, a buffer is much as it was shown with respect to FIG. 3, with the addition of an output slew rate control signal OSL used to control the output slew rate, and slew rate control circuits 402, 404.
Slew rate control is performed by the addition of n-channel transistors M5 and M6 to the pre-drive circuit driving transistor M1, and adding p-channel transistors M7 and M8 to the pre-drive circuit driving transistor M2. As shown, when the output slew rate control signal OSL is HIGH, the buffer operates at high slew rate. When the output slew rate control signal OSL is low, the buffer operates at low slew rate.
The upper slew rate control circuit 402 consists of two n-channel CMOS transistors M5, M6 connected with their drain-to-source conduction paths in parallel. M5 is a larger sized transistor used to implement the faster (high) slew rate, whereas M6 is a smaller sized transistor used to implement the slower (low) slew rate.
The gate of transistor M5 is connected to the output slew rate control signal OSL so that the gate is turned ON when the output slew rate control signal OSL is HIGH, and OFF when the output slew rate control signal OSL is LOW. An additional transistor M6, which has a very small channel width size as compared to that of transistor M5, is placed with its drain-to-source conduction path in parallel with transistor M5. The gate of transistor M6 is connected to the power supply VDD so that it is always turned ON.
The typical size of transistor M4 in the conventional buffer of FIG. 3 has a channel width of 100 um. To preserve the drive strength of the series combination of transistors M4 and M5, both transistor M4 and transistor M5 are increased to have a channel width of 200 um. This gives a drive equivalent to a single transistor having a 100 um channel width, but it increases the required fabrication area on the integrated circuit by a factor of 4 over that of an equivalent buffer not having selectable slew rate, e.g., as shown in FIG. 3.
When the output slew rate control signal OSL is HIGH, and input signal A goes HIGH, transistors M4 and M5 pull node P down quickly. This turns transistor M1 ON quickly, pulling the output signal PAD HIGH quickly. On the other hand, when the output slew rate control signal OSL is LOW, transistor M5 is turned OFF, and node P is pulled LOW through the series combination of transistors M4 and M6 when the input signal A goes HIGH. Since transistor M6 is very small, node P is pulled LOW slowly, such that transistor M1 is turned ON slowly, producing much less noise (e.g., transient noise) than if transistor M1 was turned ON by transistors M4 and M5.
Transistors M7 and M8 operate in a similar manner to control the switching speed of transistor M2. If transistor M9 in FIG. 3 had a channel width of 100 um, both it and the additional series transistor M7 must have a channel width of 200 um wide to give an equivalent drive when transistor M7 is turned ON. This too results in an area increase of a multiple of four (4) over that part of the circuit that doesn't implement slew rate selection using an output slew rate control signal OSL.
The gate of transistor M7 receives an inversion of the output slew rate control signal OSLB, which is an inverted copy of the output slew rate control signal OSL, generated by inverter X4. A p-channel transistor M8 having a very small channel width is connected in parallel with transistor M7. The gate of transistor M8 is connected to ground, so that it is always ON.
Now, when the output slew rate control signal OSL is HIGH, and input signal A goes LOW, transistor M7 is turned ON, and thus allows node N to be pulled HIGH quickly. This turns transistor M2 ON quickly, and pulls the output signal PAD LOW quickly.
When the output slew rate control signal OSL is LOW, its inverted signal OSLB is HIGH, and transistor M7 is turned OFF. Under these operating conditions, when input signal A goes LOW, node N is pulled HIGH through small transistor M8 in series with transistor M9. This means that transistor M2 will turn ON slowly, and pull the output signal PAD LOW slowly.
Because of the 4-fold area expense for portions of the buffer due to adding slew rate control to a buffer, the design of conventional buffers requires an area appreciably larger than that of buffers that do not have this feature. In the world of integrated circuits, even the smallest of savings in required area for any particular type circuit is paramount, particularly a buffer that is typically repeated many times in a given IC.
There is a need for a buffer having an adjustable slew rate design that requires less space than conventional buffers.